1. Field of the Invention
The invention relates to a semiconductor device manufacturing method, particularly, a method of manufacturing a semiconductor device having a capacitor and a MOS transistor on a same semiconductor substrate.
2. Description of the Related Art
Conventionally, a semiconductor device having a MOS transistor and a capacitor has been known. With larger scale integration of the semiconductor device developing in recent years, a shallow trench isolation method (hereafter, called a STI method) has been broadly used for isolation of an active region, replacing a method of local oxidation of silicon (LOCOS). The STI method is to fill a shallow trench in a semiconductor substrate with an insulation material such as silicon dioxide by high-density plasma chemical vapor deposition (HDPCVD) to form a field isolation film.
Hereafter, a method of manufacturing a semiconductor device having a capacitor and a high voltage MOS transistor on a same semiconductor substrate using the conventional STI method will be described with reference to figures. FIG. 8A to 10 are cross-sectional views showing the conventional method of manufacturing the semiconductor device having the capacitor and the high voltage MOS transistor on the same semiconductor substrate, showing a capacitor formation region R4.
First, as shown in FIG. 8A, STI structures where trench isolation films 50 are formed on a P-type silicon substrate 200 is formed. Next, a dummy oxide film 51 (e.g. a thermal oxidation film or a TEOS film formed by a CVD method) is formed on a front surface of the P-type silicon substrate 200 near the trench isolation films 50 to have a thickness of, for example, 5 to 10 nm.
Next, a N-type impurity, for example, arsenic ion is ion-implanted in the capacitor formation region R4 to form an lower electrode layer 52 (N+ layer) of the capacitor on the front surface of the P-type silicon substrate 200. Then, the dummy oxide film 51 is removed by etching, and a SiO2 film 53 is formed covering the front surface of the P-type silicon substrate 200 and the trench isolation films 50, to have a thickness of 20 nm, as shown in FIG. 8B. This SiO2 film 53 is to be a gate insulation film of a high voltage MOS transistor (not shown).
Since the SiO2 film 53 is too thick to be a capacitor insulation film, the SiO2 film 53 is removed by etching as shown in FIG. 9A, and then a capacitor insulation film 54 is formed by thermal oxidation to have a thickness of, for example, 7 nm, as shown in FIG. 9B.
Then, an upper electrode layer 55 formed of a polysilicon layer is formed on the capacitor insulation film 54 as shown in FIG. 10. Thus, the capacitor formed of the lower electrode layer 52, the capacitor insulation film 54, and the upper electrode layer 55 is formed.
The relevant technology is described in Japanese Patent Application Publication No. 2002-26261.
With the conventional semiconductor device manufacturing method, edges of the trench isolation films 50 are cut deep when the SiO2 film 53 is over-etched, as shown in FIG. 9A. This is because the impurity ion is implanted in the trench isolation film 50 during the ion implantation and its etching rate is higher than that without ion implantation.
Furthermore, since the impurity ion is implanted in the front surface of the P-type silicon substrate 200 in the ion implantation, accelerated oxidation occurs when the capacitor insulation film 54 is formed. Therefore, as shown in FIG. 9B, the thickness of the capacitor insulation film 54 becomes thinner at an edge portion 60 in a corner of the lower electrode layer 52.
Therefore, even if the upper electrode layer 55 is formed to form the capacitor, as shown in FIG. 10, as described above, since the thickness of the capacitor insulation film 54 has a thin portion and its thickness is uneven, there is problems that electric field concentration occurs, dielectric breakdown of the capacitor insulation film 54 easily occurs at this portion, and the life of the capacitor is short.